Parasitics in Power Electronics Packaging

In this paper we investigate the influence of 1st-level packaging components on the electromagnetic behaviour of power electronic modules. The main goal is to identify the critical layout paths and packaging components and to understand the mechanisms that affect the module performance. Several power electronics packaging technologies are compared on the basis of their electrical and electromagnetic performance and the parasitics they induce. The investigations cover the classical, widely used wire bonding as well as some new area bonding techniques such as dimple array, metal post, solder bump, flex structures, power overlay etc.. A 600V/300A IGBT module is used as a case study to illustrate the investigation results. The package analysis is done using a dedicated simulation platform based on PEEC (Partial Element Equivalent Circuit) solvers for equivalent parameter extraction (R, L, M, C).